Self-aligned via process flow

ABSTRACT

A device includes a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure generally relates to the fabrication ofsemiconductor devices, and, more particularly, to a self-aligned processflow for forming vias.

2. Description of the Related Art

In modern integrated circuits, minimum feature sizes, such as thechannel length of field effect transistors, have reached the deepsub-micron range, thereby steadily increasing performance of thesecircuits in terms of speed and/or power consumption and/or diversity ofcircuit functions. As the size of the individual circuit elements issignificantly reduced, thereby improving, for example, the switchingspeed of the transistor elements, the available floor space forinterconnect lines electrically connecting the individual circuitelements is also decreased. Consequently, the dimensions of theseinterconnect lines and the spaces between the metal lines have to bereduced to compensate for a reduced amount of available floor space andfor an increased number of circuit elements provided per unit area.

In such modern integrated circuits, a limiting factor of deviceperformance is the signal propagation delay caused by the switchingspeed of the transistor elements. As the channel length of thesetransistor elements has now reached 50 nm and less, the signalpropagation delay is no longer limited by the field effect transistors.Rather, the signal propagation delay is limited, owing to the increasedcircuit density, by the interconnect lines, since the line-to-linecapacitance (C) is increased and also the resistance (R) of the lines isincreased due to their reduced cross-sectional area. The parasitic RCtime constants and the capacitive coupling between neighboring metallines, therefore, require the introduction of a new type of material forforming the metallization layers.

Traditionally, metallization layers, i.e., the wiring layers includingmetal lines and vias for providing the electrical connection of thecircuit elements according to a specified circuit layout, are formed byembedding copper lines and vias in a dielectric layer stack. For highlysophisticated applications, in addition to using copper and/or copperalloys, the well-established and well-known dielectric materials silicondioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replacedby so-called low-k dielectric materials having a relative permittivityof approximately 3.0 and less.

In addition, the continuous reduction of the feature sizes with gatelengths of approximately 40 nm and less may demand for even more reduceddielectric constants of the corresponding dielectric materials. For thisreason, it has been proposed to introduce “air gaps,” at least atcritical device areas, since air or similar gases may have a dielectricconstant of approximately 1.0.

Process flows for forming air gaps and multiple metallization layers arecomplex. The formation of the multiple metallization layers oftenrequires the use of cap layers, such as silicon nitride, between thelayers. Since the cap layer material has a dielectric constant higherthan the low-k dielectric layer, the overall capacitance of the stack isincreased, thereby reducing the maximum achievable switching speed.

The present disclosure is directed to various methods for forming viasand resulting devices that may avoid, or at least reduce, the effects ofone or more of the problems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to an interconnectstructure. One illustrative device includes, among other things, a firstdielectric layer having at least one conductive feature embeddedtherein. A first plurality of conductive lines are embedded in a seconddielectric layer disposed above the first dielectric layer. A firstconductive line in the first plurality of conductive lines contacts theconductive feature and includes a conductive via portion and a recessedline portion. A second plurality of conductive lines are embedded in athird dielectric layer disposed above the second dielectric layer. Asecond conductive line in the second plurality of conductive linescontacts the conductive via portion and the conductive via portion has afirst cross-sectional dimension corresponding to a width of the firstconductive line and a second cross-sectional dimension corresponding toa width of the second conductive line.

Another illustrative device includes, among other things, a firstplurality of conductive lines embedded in a first dielectric layer. Afirst conductive line in the first plurality of conductive linesincludes a conductive via portion and a recessed line portion. A secondplurality of conductive lines are embedded in a second dielectric layerdisposed above the first dielectric layer. A second conductive line inthe second plurality of conductive lines contacts the conductive viaportion and the conductive via portion has a first cross-sectionaldimension corresponding to a width of the first conductive line and asecond cross-sectional dimension corresponding to a width of the secondconductive line.

Yet another illustrative device includes, among other things, a firstdielectric layer having at least one conductive feature embeddedtherein. A first plurality of conductive lines are embedded in a secondlow-k dielectric layer disposed above the first dielectric layer. Afirst conductive line in the first plurality of conductive linescontacts the conductive feature and includes a conductive via portionand a recessed line portion. A second plurality of conductive lines areembedded in a third low-k dielectric layer disposed above the secondlow-k dielectric layer. The first plurality of conductive lines areperpendicular to the second plurality of conductive lines. A secondconductive line in the second plurality of conductive lines contacts theconductive via portion and the conductive via portion has a firstcross-sectional dimension corresponding to a width of the firstconductive line and a second cross-sectional dimension corresponding toa width of the second conductive line.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1A-1M are cross-sectional views of a device depicting methodsdisclosed herein for forming vias; and

FIGS. 2A-2M are top views of the device corresponding to FIGS. 1A-1M.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure generally relates to various methods of formingvia structures and the resulting semiconductor devices. As will bereadily apparent to those skilled in the art upon a complete reading ofthe present application, the present method is applicable to a varietyof devices, including, but not limited to, logic devices, memorydevices, etc. With reference to the attached figures, variousillustrative embodiments of the methods and devices disclosed hereinwill now be described in more detail.

FIGS. 1A-1M and 2A-2M illustrate a method for forming vias in a device100 using a self-aligned process. FIGS. 1A-1M show cross-sectional viewsof the device 100 and FIGS. 2A-2M show corresponding top views of thedevice 100. The orientation of FIG. 1A is indicated by the center linein FIG. 2A. The device 100 includes a substrate 105. A dielectric layer110 is formed above the substrate 105. The dielectric layer 110 may bepart of a device layer 115 in which semiconductor-based circuit elementsmay be provided. For convenience, any such circuit elements are notshown in FIG. 1A. The substrate 105 may also include any appropriatemicrostructure features, such as micromechanical components,optoelectronic components and the like, wherein at least some of thesecomponents may require an interconnect structure formed in ametallization system. The device layer 115 includes a simplisticallydepicted conductive feature 120 (e.g., a contact) formed in thedielectric layer 110 for contacting underlying devices, such as thesource/drain regions or the gate structure of a transistor (not shown).In the case of a gate contact, the conductive feature 120 would notextend all the way to the substrate 105. A dielectric layer 125 isformed above the device layer 115 (e.g., in a Metal 1 (M1) layer). Thedielectric layer 125 may be a low-k dielectric material having adielectric constant of approximately 3.0 or lower or an ultra-low-k(ULK) material having a dielectric constant of approximately 2.5 orlower. In some embodiments, the dielectric layer 125 may be SiOC.Sacrificial lines 130 (e.g., amorphous silicon) with a cap layer 135(e.g., silicon nitride) are formed in the dielectric layer 125. Thesacrificial lines 130 may be formed by patterning a layer of material(e.g., amorphous silicon) using a patterning process (e.g., self-aligneddouble patterning (SADP), self-aligned quad patterning (SAQP), ordirected self-assembly material patterning), the specifics of which areknown to those of ordinary skill in the art. The dielectric layer 125may be deposited over the sacrificial lines 130 and planarized using thecap layer 135 as an etch stop layer. Due to the aspect ratio of theopenings defined between the sacrificial lines 130, the dielectric layer125 may not completely fill the openings, resulting in air gaps 137being formed between the sacrificial lines 130.

FIGS. 1B and 2B illustrate the device 100 after several processes wereperformed to replace the sacrificial lines 130 with conductive materialto define conductive lines 140. First, one or more etch processes wereperformed to remove the cap layer 135 and the sacrificial lines 130,resulting in the formation of recesses or openings in the dielectriclayer 125. Next, one or more deposition processes were performed so asto over-fill the recesses with a conductive material. Then, aplanarization process was performed to remove excess conductive materialpositioned above the dielectric layer 125. The conductive material mayinclude multiple layers, such as one or more barrier layers (e.g., Ta,TaN, TiN, etc.) (not separately shown) to prevent migration of any metalin the conductive lines 140 into the dielectric layer 125, a metal seedlayer (e.g., copper), and a metal fill material (e.g., copper).

FIGS. 1C and 2C illustrate the device 100 after a cap layer 145 (e.g.,silicon nitride) was formed above the dielectric layer 125. FIGS. 1D and2D illustrate the device 100 after several processes were performed toform a hard mask layer 150 (e.g., spin-on hard mask (SOH)) above the caplayer 145 and to pattern the hard mask layer 150 to define an opening155. This scheme allows for a dense pattern using a sequence ofsuccessive lithography/etch processes into layer 150 using conventionallithography, thereby avoiding the need for more complicated processes,such as EUV lithography.

FIGS. 1E and 2E illustrate the device 100 after a sacrificial material160 (e.g., amorphous carbon, DUO™ (offered commercially by Honeywell,Inc.), or any other material that can be selectively stripped from thematerial of the conductive lines 140) was formed in the opening 155 andthe hard mask layer 150 was removed. Although the sacrificial material160 is illustrated as having completely filled the opening 155, in someembodiments, the sacrificial material 160 may line the opening 155without completely filling it. For example, a layer of the sacrificialmaterial may be deposited and anisotropically etched to define spacerson sidewalls of the opening 155 and a bottom layer covering a bottomsurface of the opening 155 (as denoted by feature 165 in FIG. 1E).

FIGS. 1F and 2F illustrate the device 100 after the cap layer 145 isetched using the sacrificial material 160 as an etch mask. FIGS. 1G and2G illustrate the device 100 after a first removal process (e.g.,etching or ashing) was performed to remove the sacrificial material 160and an etch process was performed with the cap layer 145 in position todefine recessed conductive lines 140R and a conductive via portion 140V.One of the recessed conductive lines 140A interfaces with the conductivevia portion 140V. The cap layer 145 prevents recessing of the coveredportion of the conductive line 140A thereby resulting in the formationof the conductive via portion 140V. The lateral width, D1, of theconductive via portion 140V is determined by the width of thesacrificial line 130 and its length is determined by the patternedlength of the cap layer 145.

FIGS. 1H and 2H illustrate the device after several processes wereperformed to form additional dielectric material, such as additionalmaterial of the dielectric layer 125, to cover the recessed conductivelines 140R, 140A. For example, a deposition process may be performed,followed by a planarizing process or an etch process to expose theconductive via portion 140V. This process operation removes the caplayer 145.

FIGS. 1I and 2I illustrate the device 100 after performing a pluralityof processes so as to form a second set of sacrificial lines 165 with acap layer 170 formed thereabove. The orientation of FIG. 1I is indicatedby the center line in FIG. 2I. The sacrificial lines 165 are orientedperpendicularly with respect to the sacrificial lines 130 illustrated inFIG. 1A. The sacrificial lines 165 may be formed by patterning a layerof material (e.g., amorphous silicon) using a patterning process (e.g.,self-aligned double patterning (SADP), self-aligned quad patterning(SAQD), or directed self-assembly material patterning), the specifics ofwhich are known to those of ordinary skill in the art.

FIGS. 1J and 2J illustrate the device 100 after performing a recess etchon the exposed portions of the conductive via portion 140V using thesacrificial lines 165 as an etch mask. The recess etch reduces thelength, D2, of the conductive via portion 140V corresponding to thewidth of the sacrificial line 165. Thus, the horizontal cross-sectionaldimensions of the conductive via portion 140V are defined by therespective widths of the sacrificial line 130 (see FIG. 1F) and theperpendicularly orientated sacrificial line 165. The etching processesfor forming the conductive via portion 140V are self-aligned based onthe sacrificial lines 130, 165.

FIGS. 1K and 2K illustrate the device 100 after performing an optionalrecess etch of the dielectric layer 125 using the sacrificial lines 165as an etch mask. The dielectric recess etch exposes the recessed metalfeatures 140R and 140A. In some embodiments, the dielectric recess etchmay be performed prior to the conductive material recess etch describedin FIGS. 1J and 2J. In such an embodiment, further recessing of therecessed metal features 140R would occur in portions not covered by thesacrificial lines 165 during the conductive material recess etch, asthey would already be exposed. In some embodiments, the same etchprocess may be used to recess the conductive via portion 140V and thedielectric layer 125, where the etch process is not selective to theconductive material 140 compared to the dielectric layer 125.

FIGS. 1L and 2L illustrate the device 100 after performing a pluralityof processes to form a second dielectric layer 175 (e.g., in a Metal 2(M2) layer). The dielectric layer 175 may be deposited to extend abovethe sacrificial lines 165 and a planarization process or a recess etchmay be performed to remove the portion extending above the sacrificiallines 165. Due to the aspect ratio of the openings defined between thesacrificial lines 165, the dielectric layer 175 may not completely fillthe openings, resulting in air gaps 180 between the sacrificial lines165. The air gaps 180 reduce the capacitance of the device 100, therebyincreasing switching speed, and as a result, performance. The use of thedielectric etch process illustrated in FIGS. 1K and 2K increases thesize of the air gaps 180.

FIGS. 1M and 2M illustrate the device 100 after several processes wereperformed to replace the sacrificial lines 165 with conductive materialto define conductive lines 185. First, one or more etch processes wereperformed to remove the cap layer 170 and the sacrificial lines 165,resulting in recesses. Next, one or more deposition processes wereperformed so as to over-fill the recesses with a conductive material.Then, a planarization process was performed to remove excess conductivematerial. The conductive lines 185 may include multiple layers, such asone or more barrier layers (e.g., Ta, TaN, TiN, etc.) to preventmigration of any metal in the conductive lines 185 into the dielectriclayer 175, a metal seed layer (e.g., copper), and a metal fill material(e.g., copper). One of the conductive lines 185A interfaces with theconductive via portion 140V. Thus, the conductive via portion 140Vconnects the conductive line 140A in the M1 layer to the conductive line185A in the M2 layer.

Subsequent processes may be performed to complete the fabrication of thedevice 100, such as forming additional metallization layers, diesingulation, and packaging. The use of the illustrated process providesself-aligned control of the via formation process. The use of thesacrificial lines 130, 165 prevents via misalignment in both the x and ydirections. The use of the sacrificial material 160 to pattern the caplayer 145 allows the cap layer 145 to be completely removed from betweenthe first and second dielectric layers 125, 175, thereby reducing thecapacitance of the device 100.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Note that the use of terms, such as “first,” “second,”“third” or “fourth” to describe various processes or structures in thisspecification and in the attached claims is only used as a shorthandreference to such steps/structures and does not necessarily imply thatsuch steps/structures are performed/formed in that ordered sequence. Ofcourse, depending upon the exact claim language, an ordered sequence ofsuch processes may or may not be required. Accordingly, the protectionsought herein is as set forth in the claims below.

What is claimed:
 1. A device, comprising: a first dielectric layerhaving at least one conductive feature embedded therein; a firstplurality of conductive lines embedded in a second dielectric layerdisposed above said first dielectric layer, wherein a first conductiveline in said first plurality of conductive lines contacts saidconductive feature and comprises a conductive via portion and a recessedline portion; and a second plurality of conductive lines embedded in athird dielectric layer disposed above said second dielectric layer,wherein a second conductive line in said second plurality of conductivelines contacts said conductive via portion and said conductive viaportion has a first cross-sectional dimension corresponding to a widthof said first conductive line and a second cross-sectional dimensioncorresponding to a width of said second conductive line.
 2. The deviceof claim 1, wherein said second dielectric layer has a reduced thicknessin a region disposed beneath each of said second plurality of conductivelines, and the device further comprises air gaps disposed in said thirddielectric layer between pairs of adjacent second conductive lines. 3.The device of claim 1, further comprising air gaps disposed in saidsecond dielectric layer between pairs of adjacent second conductivelines.
 4. The device of claim 1, wherein said first plurality ofconductive lines are perpendicular to said second plurality ofconductive lines.
 5. The device of claim 1, wherein said thirddielectric layer directly contacts said second dielectric layer.
 6. Thedevice of claim 5, wherein said second and third dielectric layerscomprise low-k dielectric materials.
 7. A device, comprising: a firstplurality of conductive lines embedded in a first dielectric layer,wherein a first conductive line in said first plurality of conductivelines comprises a conductive via portion and a recessed line portion;and a second plurality of conductive lines embedded in a seconddielectric layer disposed above said first dielectric layer, wherein asecond conductive line in said second plurality of conductive linescontacts said conductive via portion and said conductive via portion hasa first cross-sectional dimension corresponding to a width of said firstconductive line and a second cross-sectional dimension corresponding toa width of said second conductive line.
 8. The device of claim 7,wherein said first dielectric layer has a reduced thickness in a regiondisposed beneath each of said second plurality of conductive lines, andthe device further comprises air gaps disposed in said second dielectriclayer between pairs of adjacent second conductive lines.
 9. The deviceof claim 7, further comprising air gaps disposed in said firstdielectric layer between pairs of adjacent second conductive lines. 10.The device of claim 7, wherein said first plurality of conductive linesare perpendicular to said second plurality of conductive lines.
 11. Thedevice of claim 7, wherein said second dielectric layer directlycontacts said first dielectric layer.
 12. The device of claim 11,wherein said first and second dielectric layers comprise low-kdielectric materials.
 13. A device, comprising: a first dielectric layerhaving at least one conductive feature embedded therein; a firstplurality of conductive lines embedded in a second low-k dielectriclayer disposed above said first dielectric layer, wherein a firstconductive line in said first plurality of conductive lines contactssaid conductive feature and includes a conductive via portion and arecessed line portion; and a second plurality of conductive linesembedded in a third low-k dielectric layer disposed above said secondlow-k dielectric layer, wherein said first plurality of conductive linesare perpendicular to said second plurality of conductive lines, saidthird low-k dielectric layer directly contacts said second low-kdielectric layer, a second conductive line in said second plurality ofconductive lines contacts said conductive via portion, and saidconductive via portion has a first cross-sectional dimensioncorresponding to a width of said first conductive line and a secondcross-sectional dimension corresponding to a width of said secondconductive line.
 14. The device of claim 13, wherein said second low-kdielectric layer has a reduced thickness in a region disposed beneatheach of said second plurality of conductive lines, and the devicefurther comprises air gaps disposed in said third low-k dielectric layerbetween pairs of adjacent second conductive lines.
 15. The device ofclaim 13, further comprising air gaps disposed in said second low-kdielectric layer between pairs of adjacent second conductive lines.